The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Nov. 28, 2018
Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventors:

Akio Kitamura, Matsumoto, JP;

Shinichiro Adachi, Matsumoto, JP;

Nobuhide Arai, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/473 (2006.01); H01L 25/07 (2006.01); H01L 23/373 (2006.01); H01L 25/18 (2006.01); H01L 23/532 (2006.01); H01L 27/07 (2006.01);
U.S. Cl.
CPC ...
H01L 23/473 (2013.01); H01L 23/3735 (2013.01); H01L 23/53209 (2013.01); H01L 25/07 (2013.01); H01L 25/18 (2013.01); H01L 27/0711 (2013.01);
Abstract

Provided is a semiconductor module comprising: a semiconductor chip; a cooling portion having a refrigerant passing portion through which a refrigerant passes; and a laminated substrate having: a first metal interconnection layer; a second metal interconnection layer; and an insulation provided between the first metal interconnection layer and the second metal interconnection layer, wherein the cooling portion has: a top plate; a bottom plate; and a plurality of protruding parts which are provided on a surface of the bottom plate, and are separated from each other in a flow direction of the refrigerant, and are respectively provided continuously in a direction orthogonal to the flow direction, wherein the plurality of protruding parts are provided at a position overlapping with one end of the second metal interconnection layer and at a position overlapping with the semiconductor chip in the flow direction.


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