The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Oct. 24, 2018
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Marcella Carissimi, Treviolo, IT;

Marco Pasotti, Travaco' Siccomario, IT;

Chantal Auricchio, Cassina de' Pecchi, IT;

Assignee:

STMicroelectronics S.R.L., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 45/00 (2006.01); G11C 5/02 (2006.01); H01L 27/24 (2006.01); G11C 17/12 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0004 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); G11C 17/12 (2013.01); H01L 27/2436 (2013.01); H01L 45/06 (2013.01); G11C 2213/79 (2013.01);
Abstract

The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.


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