The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Apr. 03, 2019
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Andres Felipe Hernandez Mojica, Seattle, WA (US);

William Paul Hovis, Sammamish, WA (US);

Garrett Douglas Blankenburg, Sammamish, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 1/00 (2006.01); G06F 9/44 (2018.01); G06F 13/10 (2006.01); G06F 13/12 (2006.01); G06F 30/392 (2020.01); G06F 11/30 (2006.01); G06F 30/3308 (2020.01); G06F 30/337 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 1/00 (2013.01); G06F 9/44 (2013.01); G06F 11/30 (2013.01); G06F 13/10 (2013.01); G06F 13/12 (2013.01); G06F 30/337 (2020.01); G06F 30/3308 (2020.01); G06F 30/398 (2020.01);
Abstract

Computing assemblies, such as blade servers, can comprise a plurality of modular computing elements coupled onto an associated circuit board assembly. Assemblies and systems having enhanced individual computing module placement and arrangement are discussed herein, as well as example systems and operations to manufacture such assemblies. In one example, a method includes executing a performance test on a plurality of computing modules to determine at least variability in power consumption across the plurality of computing modules, and binning the plurality of computing modules according to graduated levels of the variability in power consumption. The method also includes selecting from among the graduated levels for placement in an assembly of ones of the computing modules in a progressively lower power consumption arrangement with relation to an airflow of the assembly.


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