The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2020
Filed:
Apr. 19, 2018
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventor:
Danny Bradley, Austin, TX (US);
Assignee:
Other;
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/3312 (2020.01); G06F 30/327 (2020.01); G06F 30/337 (2020.01); G06F 30/396 (2020.01); G06F 119/12 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/327 (2020.01); G06F 30/337 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01);
Abstract
During logic synthesis and placement optimization, designs are aggressively optimized for timing, power, and area but only the data paths are modified and the clock network is assumed to be 'ideal' and fixed. The described embodiments optimize the clock network as well as the data path logic during the logic synthesis and placement optimization stages, thereby improving the overall performance of the design.
Bradley, Danny. (2020). Optimization after allocating potential slacks to clock arrival times (U.S. Patent No. 10755009). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10755009
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile