The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2020
Filed:
Sep. 25, 2018
Northrop Grumman Systems Corporation, Falls Church, VA (US);
Kenneth R. Weidele, San Diego, CA (US);
Kenneth F. McKinney, San Diego, CA (US);
Christopher H. Meawad, Washington, DC (US);
Tim Manestitaya, San Diego, CA (US);
Allan T. Hilchie, Sierra Vista, AZ (US);
Timothy D. Schaffner, Santee, CA (US);
NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);
Abstract
A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal time in each mode over the system's lifecycle. A configuration memory (CM) input inversion plane is positioned between a CM controller and the CM cells, and a CM output inversion plane is positioned between the CM cells and the FPGA function blocks. When running in inversion mode, data to/from the CM cells is inverted (0's and 1's are swapped) by the input and output inversion planes. By balancing time individual memory addresses spend in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as a processor's external RAM and internal cache, is also disclosed.