The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Nov. 15, 2017
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Andrew William Berner, Waterford, NY (US);

Tab Mong, Erie, PA (US);

Richard Gawrelski, Amsterdam, NY (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 9/455 (2018.01); G06F 11/34 (2006.01); G06F 16/2458 (2019.01); G05B 23/00 (2006.01); G06F 15/78 (2006.01); G06F 11/00 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3013 (2013.01); G05B 23/00 (2013.01); G06F 9/45558 (2013.01); G06F 11/3003 (2013.01); G06F 11/3058 (2013.01); G06F 11/3089 (2013.01); G06F 11/3452 (2013.01); G06F 15/7867 (2013.01); G06F 16/2465 (2019.01); G06F 11/008 (2013.01); G06F 11/0754 (2013.01); G06F 2009/45591 (2013.01); G06F 2201/815 (2013.01);
Abstract

The example embodiments are directed to a system and method for a virtual processor that enables unobtrusive observation of legacy systems for analytics in a system-on-chip (SoC) environment. In one example, the method includes implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system, capturing one or more operational parameters in volatile memory of the virtual processor using an access controller configured to provide direct access to the volatile memory of the virtual processor, streaming the one or more operational parameters to the embedded processor, storing the one or more operational parameters in volatile memory of the embedded processor, and performing in-situ monitoring using the one or more operational parameters.


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