The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Dec. 17, 2018
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Alex James Waugh, Cambridge, GB;

Pedro López Muñoz, Cambridge, GB;

Peng Wang, Cambridge, GB;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/22 (2006.01); G06F 11/36 (2006.01); G01R 31/317 (2006.01); G06F 16/903 (2019.01); G06F 11/30 (2006.01); G06F 11/26 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2236 (2013.01); G01R 31/31705 (2013.01); G06F 11/26 (2013.01); G06F 11/3072 (2013.01); G06F 16/903 (2019.01);
Abstract

At least one processor core has debug and non-debug modes of operation. Debug control circuitry controls operation of the at least one processor core when in the debug mode. On power up of a given processor core, the core checks a debug status value stored in a debug status storage element. When the debug status value has a first value, a debug connect sequence of messages is exchanged with the debug control circuitry over a debug interface to determine whether the given processor core should operate in the debug mode or the non-debug mode, and the debug status value is set to a second value when it is determined that the given processor core should operate in the non-debug mode. When the debug status value has the second value, the given processor core omits initiating the debug connect sequence and determines that it should operate in the non-debug mode.


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