The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Mar. 13, 2019
Applicant:

Ambarella International Lp, Santa Clara, CA (US);

Inventors:

Xuan Wang, San Jose, CA (US);

Jingxiao Li, San Jose, CA (US);

Tianwei Liu, Fremont, CA (US);

Yuan-Fu Lin, Santa Clara, CA (US);

Assignee:

Ambarella International LP, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/04 (2006.01); H03M 1/66 (2006.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
H04L 7/04 (2013.01); H03L 7/0807 (2013.01); H03M 1/66 (2013.01);
Abstract

An apparatus includes a slicer circuit, a frequency acquisition circuit, a phase acquisition circuit and an oscillator circuit. The slicer circuit may be configured to (i) generate an output signal by slicing a data signal in response to a clock signal and (ii) generate a crossing signal in response to the data signal and the clock signal. The frequency acquisition circuit may be configured to generate a first control signal and a second control signal in response to the data signal and the clock signal. The phase acquisition circuit may be configured to generate a third control signal in response to the first control signal and the data crossing signal. The oscillator circuit may be configured to generate the clock signal in response to the second control signal and the third control signal. The second control signal may shift an adjustable frequency range of the clock signal.


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