Method and apparatus for simultaneous propagation of multiple clockfrequencies in serializer/deserializer (serdes) macros

Abstract

The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency fencoded in differential mode, a second PLL configured to generate a second high-speed clock frequency fencoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency fand the common mode encoding the second high-speed clock frequency fand transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.