The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Nov. 16, 2018
Applicant:

Ayar Labs, Inc., Emeryville, CA (US);

Inventors:

Chen Sun, Berkeley, CA (US);

Roy Edward Meade, Boise, ID (US);

Mark Wade, Oakland, CA (US);

Alexandra Wright, San Francisco, CA (US);

Vladimir Stojanovic, Berkeley, CA (US);

Rajeev Ram, San Francisco, CA (US);

Milos Popovic, San Francisco, CA (US);

Derek Van Orden, San Francisco, CA (US);

Michael Davenport, San Francisco, CA (US);

Assignee:

Ayar Labs, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); H04B 10/50 (2013.01); H01S 5/022 (2006.01); H01S 5/40 (2006.01); H01S 5/026 (2006.01); H04B 10/80 (2013.01); H01S 5/024 (2006.01); H01S 5/50 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
H04B 10/504 (2013.01); H01S 5/0268 (2013.01); H01S 5/02248 (2013.01); H01S 5/4012 (2013.01); H01S 5/4087 (2013.01); H04B 10/506 (2013.01); H04B 10/801 (2013.01); G02B 6/42 (2013.01); H01S 5/02476 (2013.01); H01S 5/50 (2013.01);
Abstract

An interposer device includes a substrate that includes a laser source chip interface region, a silicon photonics chip interface region, an optical amplifier module interface region. A fiber-to-interposer connection region is formed within the substrate. A first group of optical conveyance structures is formed within the substrate to optically connect a laser source chip to a silicon photonics chip when the laser source chip and the silicon photonics chip are interfaced to the substrate. A second group of optical conveyance structures is formed within the substrate to optically connect the silicon photonics chip to an optical amplifier module when the silicon photonics chip and the optical amplifier module are interfaced to the substrate. A third group of optical conveyance structures is formed within the substrate to optically connect the optical amplifier module to the fiber-to-interposer connection region when the optical amplifier module is interfaced to the substrate.


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