The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2020
Filed:
May. 08, 2019
Applicant:
Chaoyang Semiconductor Jiangyin Technology Co., Ltd., Jiangyin, CN;
Inventor:
Hassan Ihs, San Diego, CA (US);
Assignee:
Chaoyang Semiconductor Jiangyin Technology Co., Ltd., Jiangyin, Jiangsu Province, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/15 (2006.01); G05F 1/565 (2006.01); G01R 19/165 (2006.01); G05F 3/08 (2006.01); H02M 3/155 (2006.01); H03L 7/089 (2006.01); H03K 5/1252 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/15 (2013.01); G01R 19/165 (2013.01); G01R 19/16552 (2013.01); G05F 1/565 (2013.01); G05F 3/08 (2013.01); H02M 3/155 (2013.01); H03L 7/0891 (2013.01); H03K 5/1252 (2013.01); H03K 2005/00019 (2013.01);
Abstract
Droop monitors spread across a system-on-chip (SoC) monitor for voltage droops in regulated supply voltage supplied to logic circuitry of the SoC. In the event of a voltage droop, a clock signal supplied to the logic circuitry is stretched, to temporarily increase a period of the clock signal. The droop monitors may include a sensing delay line provided voltage at the regulated supply voltage, and a reference delay line supplied with a reference voltage, with operations of the delay lines monitored to determine a voltage droop.