The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Mar. 30, 2018
Applicant:

Dynax Semiconductor, Inc., Kunshan, Jiangsu Province, CN;

Inventors:

Yi Pei, Kunshan, CN;

Feihang Liu, Kunshan, CN;

Assignee:

DYNAX SEMICONDUCTOR, INC., Kunshan, Jiangsu Province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/778 (2006.01); H01L 21/765 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/402 (2013.01); H01L 21/765 (2013.01); H01L 29/2003 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01);
Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. A semiconductor device according to a performing mode includes a substrate, a semiconductor layer located on one side of the substrate, a source and a drain located on one side of the semiconductor layer away from the substrate, and a gate located between the source and the drain, and an isolation structure disposed on one side of the semiconductor layer away from the substrate, one end of the isolation structure being disposed at a side close to the source, and the other end being disposed at a side close to the drain and in direct contact with the surface layer of the semiconductor device, the isolation structure covering the gate or a part of the gate, the isolation structure being an integrally formed structure and forming a chamber with the semiconductor layer.


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