The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Nov. 12, 2019
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventor:

Martin Domeij, Sollentuna, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 21/308 (2006.01); H01L 29/10 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/308 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 29/1033 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01); H01L 27/0927 (2013.01);
Abstract

A semiconductor device includes a source region configured to provide at least a portion of a MOSFET source of a MOSFET and at least a portion of a JFET source of a JFET. The semiconductor device includes a JFET channel region in series with the source region and a MOSFET channel region of the MOSFET, and disposed between a first JFET gate and a second JFET gate. The semiconductor device includes a JFET drain disposed at least partially between a gate insulator of a gate of the MOSFET and at least a portion of the JFET channel region, and in electrical contact with the first JFET gate and the second JFET gate. Various example implementations of this type of semiconductor device provide a SiC power MOSFET with improved short-circuit capability and durability, with minimal impact on R.


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