The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Dec. 04, 2018
Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventors:

Takayuki Hirose, Kanagawa, JP;

Yutaka Terao, Tokyo, JP;

Aki Takigawa, Tokyo, JP;

Etsuko Tomita, Tokyo, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 21/66 (2006.01); H01L 21/04 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/34 (2006.01); G01N 21/3581 (2014.01); G01N 21/84 (2006.01); H01L 21/02 (2006.01); G01N 21/41 (2006.01); G01R 31/265 (2006.01); G01Q 60/30 (2010.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); G01N 21/3581 (2013.01); G01N 21/41 (2013.01); G01N 21/84 (2013.01); G01Q 60/30 (2013.01); G01R 31/2656 (2013.01); H01L 21/02378 (2013.01); H01L 21/049 (2013.01); H01L 22/14 (2013.01); H01L 22/20 (2013.01); H01L 22/24 (2013.01); H01L 29/34 (2013.01); H01L 29/66068 (2013.01); H01L 29/78 (2013.01); H01L 29/7813 (2013.01); G01N 2021/4186 (2013.01); G01N 2021/8461 (2013.01); H01L 22/12 (2013.01);
Abstract

A method of evaluating an insulated-gate semiconductor device having an insulated-gate structure including a channel formation layer made of a wide-bandgap semiconductor and a gate insulating film formed contacting the channel formation layer includes removing the gate insulating film in order to expose a surface of the channel formation layer; taking a phase image of the exposed surface of the channel formation layer using a phase mode of an atomic force microscope; evaluating a surface condition of the exposed surface of the channel formation layer by calculating an evaluation metric from phase shift values in the phase image and by determining whether the evaluation metric satisfies a prescribed condition; and determining that the insulated-gate semiconductor device is acceptable when the evaluation metric satisfied the prescribed condition.


Find Patent Forward Citations

Hirose, Takayuki. (2020). Method of evaluating insulated-gate semiconductor device (U.S. Patent No. 10749001). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10749001

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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