The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Nov. 06, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yasuhiro Yadoguchi, Tokyo, JP;

Takashi Fujii, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/118 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11807 (2013.01); H01L 27/0207 (2013.01); H03K 19/1736 (2013.01); H01L 2027/1182 (2013.01); H01L 2027/1187 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11881 (2013.01); H01L 2027/11885 (2013.01);
Abstract

Provided is a semiconductor device in which influence resulting from a cell function change can be reduced. The semiconductor device includes a function cell designed using a basic cell including a first wiring layer provided over a main surface of a semiconductor substrate and having a predetermined pattern and a second wiring layer provided over the first wiring layer and having a predetermined pattern. The function cell corresponds to the basic cell which is modified to have a predetermined function by changing the pattern of the second wiring layer at a design stage. The function cell has a first layout and a second layout which are disposed in juxtaposition in one direction in a plane parallel with the main surface. The function cell is provided with the predetermined function by coupling together wires belonging to the respective second wiring layers of the first layout and the second layout.


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