The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2020
Filed:
Mar. 09, 2018
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Se Hun Kang, Gyeonggi-do, KR;
Deok Sin Kil, Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11585 (2017.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/1159 (2017.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11585 (2013.01); H01L 27/1159 (2013.01); H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09);
Abstract
A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. The ferroelectric layers may be formed in the recess. The source may be arranged at a first side of the recess. The drain may be arranged at a second side of the recess opposite to the first side. The gate may be arranged on the ferroelectric layers. The ferroelectric layers may be polarized by different electric fields.