The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Mar. 12, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kota Nishikawa, Kawasaki, JP;

Hiroshi Tsubouchi, Yokohama, JP;

Kenri Nakai, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); H01L 27/11582 (2017.01); H01L 23/528 (2006.01); G11C 16/08 (2006.01); H01L 27/1157 (2017.01); G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); H01L 27/11573 (2017.01); H01L 29/10 (2006.01); G11C 11/56 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 23/528 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 29/1037 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.


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