The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2020
Filed:
Sep. 25, 2018
Northrop Grumman Systems Corporation, Falls Church, VA (US);
Kenneth R. Weidele, San Diego, CA (US);
Kenneth F. McKinney, San Diego, CA (US);
Christopher H. Meawad, Washington, DC (US);
Tim Manestitaya, San Diego, CA (US);
Allan T. Hilchie, Sierra Vista, AZ (US);
Timothy D. Schaffner, Santee, CA (US);
NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);
Abstract
A method and architecture for mitigating memory imprinting in electronic system volatile memory. At system power-up, a bus mode register control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal amounts of time in each mode over the system's lifecycle. A bi-directional data bus inverter is positioned between a system processor and volatile memory. When the system is running in inversion mode, data from non-volatile memory is inverted (0's and 1's are swapped) when copied to volatile memory, and the data bus inverter rectifies all data bits flowing in/out of the processor. By balancing the time spent by individual memory addresses in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as internal processor cache memory, and FPGA configuration memory, is also disclosed.