The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2020
Filed:
Jan. 15, 2018
Applicant:
Microchip Technology Incorporated, Chandler, AZ (US);
Inventors:
Assignee:
MICROCHIP TECHNOLOGY INCORPORATED, Chandler, AZ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G11C 29/02 (2006.01); G11C 29/08 (2006.01); G11C 29/36 (2006.01); G11C 29/10 (2006.01); G11C 29/12 (2006.01); G11C 29/34 (2006.01); G11C 29/38 (2006.01); G11C 29/52 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 29/04 (2006.01); G06F 11/08 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0796 (2013.01); G06F 3/0614 (2013.01); G06F 3/0629 (2013.01); G06F 13/1689 (2013.01); G11C 29/022 (2013.01); G11C 29/08 (2013.01); G11C 29/10 (2013.01); G11C 29/12 (2013.01); G11C 29/1201 (2013.01); G11C 29/34 (2013.01); G11C 29/36 (2013.01); G11C 29/38 (2013.01); G11C 29/52 (2013.01); G06F 3/061 (2013.01); G06F 11/08 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/3602 (2013.01);
Abstract
A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.