The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Aug. 30, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Mattheus Cornelis Antonius Adrianus Heddes, Woodinville, WA (US);

Natarajan Vaidhyanathan, Carrboro, NC (US);

Robert Dreyer, Menlo Park, CA (US);

Colin Beaton Verrilli, Apex, NC (US);

Koustav Bhattacharya, Austin, TX (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/483 (2006.01); G06F 7/544 (2006.01); G06F 15/80 (2006.01); G06F 7/499 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 7/483 (2013.01); G06F 7/49936 (2013.01); G06F 7/5443 (2013.01); G06F 15/8092 (2013.01); G06F 15/7807 (2013.01);
Abstract

Providing efficient floating-point operations using matrix processors in processor-based systems is disclosed. In this regard, a matrix-processor-based device provides a matrix processor comprising a positive partial sum accumulator and a negative partial sum accumulator. As the matrix processor processes pairs of floating-point operands, the matrix processor calculates an intermediate product based on a first floating-point operand and a second floating-point operand and determines a sign of the intermediate product. Based on the sign, the matrix processor normalizes the intermediate product with a partial sum fraction of the positive partial sum accumulator or the negative partial sum accumulator, then adds the intermediate product to the positive sum accumulator or the negative sum accumulator. After processing all pairs of floating-point operands, the matrix processor subtracts the negative partial sum accumulator from the positive partial sum accumulator to generate a final sum, then renormalizes the final sum a single time.


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