The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Mar. 06, 2015
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Tatsuya Zettsu, Yokohama Kanagawa, JP;

Katsuhiko Ueki, Tokyo, JP;

Yoshihisa Kojima, Kawasaki Kanagawa, JP;

Hiroshi Yao, Yokohama Kanagawa, JP;

Kenichiro Yoshii, Tokyo, JP;

Ikuo Magaki, Kawasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 3/0634 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); Y02D 10/154 (2018.01);
Abstract

According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.


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