The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Jul. 31, 2019
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

Houle Gan, Santa Clara, CA (US);

Mikhail Popovich, Danville, CA (US);

Shuai Jiang, Saratoga, CA (US);

Gregory Sizikov, Sunnyvale, CA (US);

Chee Yee Chung, Milpitas, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H03K 17/687 (2006.01); G06F 1/26 (2006.01); H02M 3/07 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); G06F 1/263 (2013.01); H02M 3/07 (2013.01);
Abstract

An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connector of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.


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