The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Sep. 13, 2018
Applicant:

Arista Networks, Inc., Santa Clara, CA (US);

Inventors:

Robert Wilcox, Santa Clara, CA (US);

Richard Hibbs, Santa Clara, CA (US);

Youngbae Park, Santa Clara, CA (US);

Cliff Willis, Santa Clara, CA (US);

Aravind Musunuri, Santa Clara, CA (US);

Assignee:

ARISTA NETWORKS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01R 12/55 (2011.01); H01R 12/52 (2011.01); H01R 12/51 (2011.01); H01R 12/53 (2011.01);
U.S. Cl.
CPC ...
H01R 12/55 (2013.01); H01R 12/515 (2013.01); H01R 12/523 (2013.01); H01R 12/53 (2013.01);
Abstract

In one embodiment, an apparatus is provided. The apparatus includes a printed circuit board (PCB). The apparatus also includes a first dual stacked octal small format pluggable (OSFP) module coupled to the PCB on a top surface of the PCB. The first dual stacked OSFP module comprises two OSFP modules that are vertically stacked. The apparatus further includes a second dual stacked OSFP module coupled to the PCB on a bottom surface of the PCB. The second dual stacked OSFP module comprises two OSFP modules that are vertically stacked. A first bottom of the first dual stacked OSFP module is flush against the top surface of the PCB. A second bottom of the second dual stacked OSFP is flush against the bottom surface of the PCB.


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