The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Jun. 26, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Dong-hun Lee, Anyang-si, KR;

Dong-won Kim, Seongnam-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); G11C 11/419 (2006.01); H01L 27/146 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 27/11578 (2017.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); G11C 11/419 (2013.01); H01L 21/02603 (2013.01); H01L 21/02606 (2013.01); H01L 27/1104 (2013.01); H01L 27/14616 (2013.01); H01L 29/0665 (2013.01); H01L 29/0669 (2013.01); H01L 29/0673 (2013.01); H01L 29/1025 (2013.01); H01L 29/42392 (2013.01); H01L 27/11578 (2013.01); H01L 29/1037 (2013.01); H01L 29/66787 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.


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