The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Dec. 10, 2018
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Yu-Gwang Jeong, Anyang-si, KR;

Hyun Min Cho, Hwaseong-si, KR;

Su Bin Bae, Gyeongsan-si, KR;

Shin Il Choi, Hwaseong-si, KR;

Sang Gab Kim, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/311 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01); G02F 1/1368 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 27/1218 (2013.01); H01L 27/1288 (2013.01); H01L 29/41733 (2013.01); H01L 29/78633 (2013.01); G02F 1/1368 (2013.01); G02F 2201/123 (2013.01); H01L 27/3246 (2013.01); H01L 27/3248 (2013.01); H01L 27/3262 (2013.01); H01L 27/3276 (2013.01);
Abstract

A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.


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