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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10741572 B1

PDFFull Text
Date of Patent:
Aug. 11, 2020

Filed:

Jun. 15, 2017

Three-dimensional memory device having multilayer word lines containing selectively grown cobalt or ruthenium and method of making the same

Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Rahul Sharangpani, Fremont, CA (US);

Raghuveer Makala, Campbell, CA (US);

Yanli Zhang, San Jose, CA (US);

Yao-Sheng Lee, Tampa, FL (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

The Marbury Law Group, PLLC

Primary Examiner:

Matthew L Reames

Assistant Examiner:

John A Bodnar

Int. Cl.
CPC ...
H01L 27/30 (2006.01); H01L 27/148 (2006.01); H01L 51/44 (2006.01); H01L 51/42 (2006.01); H04N 5/372 (2011.01); H01L 27/1157 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 23/532 (2006.01); H01L 27/11573 (2017.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 27/11526 (2017.01); H01L 27/11548 (2017.01); H01L 27/11575 (2017.01); H01L 27/11582 (2017.01); H01L 29/49 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 23/5226 (2013.01); H01L 23/53266 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01);
Abstract

A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.

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