The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2020
Filed:
Apr. 02, 2019
Applicant:
Presidio Components. Inc., San Diego, CA (US);
Inventors:
Hung Van Trinh, La Jolla, CA (US);
Alan Devoe, La Jolla, CA (US);
Assignee:
Presidio Components. Inc., San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/35 (2006.01); H01G 4/005 (2006.01); H01G 4/30 (2006.01); H01G 4/012 (2006.01);
U.S. Cl.
CPC ...
H01G 4/35 (2013.01); H01G 4/005 (2013.01); H01G 4/012 (2013.01); H01G 4/30 (2013.01);
Abstract
A multilayer chip capacitor includes electrodes comprised of numerous, closely spaced conductive layers. Adjacent conductive layers are essentially non-overlapping, so that fringe capacitance between opposing electrodes provides substantially all of the capacitance. The conductive layers may be shaped to form a non-planer boundary between electrodes. An additional high frequency integrated capacitor is formed from external electrode plates. The non-planar electrode boundary principle is also applied to discoidal capacitors in the form of a non-concentric electrode boundary.