The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2020
Filed:
Apr. 17, 2018
Applicant:
Sandisk Technologies Llc, Plano, TX (US);
Inventors:
Mohan V Dunga, Santa Clara, CA (US);
Pitamber Shukla, Milpitas, CA (US);
Assignee:
SanDisk Technologies LLC, Addison, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/04 (2006.01); G11C 16/10 (2006.01); G11C 13/00 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 29/50 (2006.01); G11C 8/08 (2006.01); G11C 29/02 (2006.01); G11C 29/00 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/24 (2006.01); G11C 7/10 (2006.01); G11C 29/42 (2006.01); G11C 29/12 (2006.01); G11C 8/14 (2006.01); G11C 7/18 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 8/08 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 29/028 (2013.01); G11C 29/50012 (2013.01); G11C 7/1015 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 29/42 (2013.01); G11C 29/838 (2013.01); G11C 2013/0085 (2013.01); G11C 2013/0092 (2013.01); G11C 2029/1202 (2013.01); G11C 2213/71 (2013.01); H01L 27/1157 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 27/249 (2013.01);
Abstract
A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.