The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Aug. 10, 2017
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Xinsheng Optoelectronics Technology Co., Ltd., Hefei, Anhui, CN;

Inventors:

Mo Chen, Beijing, CN;

Jinliang Liu, Beijing, CN;

Wuxia Fu, Beijing, CN;

Huanyu Li, Beijing, CN;

Songmei Sun, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); G09G 3/20 (2006.01); G06F 1/10 (2006.01); G06F 1/26 (2006.01); G09G 3/3266 (2016.01);
U.S. Cl.
CPC ...
G09G 3/36 (2013.01); G06F 1/10 (2013.01); G06F 1/26 (2013.01); G09G 3/20 (2013.01); G11C 19/28 (2013.01); G09G 3/3266 (2013.01); G09G 3/3674 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0283 (2013.01); G09G 2310/0286 (2013.01); G11C 19/287 (2013.01);
Abstract

A shift register circuit is disclosed that includes an input control circuit configured to set a first node at a first potential in response to an active pulse signal from a signal input terminal, an output control circuit configured to supply a clock signal from a first clock signal terminal to a signal output terminal in response to the first node being at the first potential, the first potential being less than a potential of the active pulse signal and greater than or equal to a potential for maintaining operation of the output control circuit, and a reset circuit configured to supply a reference voltage from a reference voltage terminal to the first node and the signal output terminal in response to a reset signal.


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