The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Jul. 12, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventor:

Matthew H. Klein, Redwood City, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/34 (2020.01); G06F 30/373 (2020.01); G06F 115/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/34 (2020.01); G06F 30/373 (2020.01); G06F 2115/02 (2020.01);
Abstract

A programmable logic device includes an integrated circuit die having a programmable fabric region including N identical programmable logic partitions. In some embodiments, N−1 of the identical programmable logic partitions are user-programmable. In addition, and in some cases, one of the identical programmable logic partitions is a spare logic partition. In some embodiments, the integrated circuit die further includes a network-on-a-chip (NOC) including a vertical NOC (VNOC) and a horizontal NOC (HNOC). By way of example, the N identical programmable logic partitions are configured to communicate exclusively through the NOC. In some embodiments, a defective one of the N−1 identical programmable logic partitions is configured for swapping with the spare logic partition.


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