The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Jul. 19, 2010
Applicants:

Aaron Marking, Portland, OR (US);

Kenneth Goeller, Los Angeles, CA (US);

Jeffrey Bruce Lotspiech, Henderson, NV (US);

Inventors:

Aaron Marking, Portland, OR (US);

Kenneth Goeller, Los Angeles, CA (US);

Jeffrey Bruce Lotspiech, Henderson, NV (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/44 (2013.01); G06F 21/10 (2013.01); H04K 1/00 (2006.01); H04L 29/08 (2006.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/44 (2013.01); G06F 21/10 (2013.01); H04K 1/00 (2013.01); H04L 63/0428 (2013.01); H04L 67/06 (2013.01); H04L 67/108 (2013.01); H04L 67/104 (2013.01); H04L 2209/60 (2013.01);
Abstract

A playback device includes a port configured to receive content from an external memory device, a device memory residing in the device, and a controller programmed to execute instructions that cause the controller to read a read data pattern from the defined region in the external memory device and determine if the read data pattern correlates to an expected data pattern to a predetermined level, wherein the expected data pattern is derived at least in part from a defect map of the defined region. A memory device includes an array of memory cells configured to store at least one bit of data, the array of memory cells being organized into regions, at least one first region of the array of memory cells having stored therein a defect map of the array of memory cells, and at least one second region of the array of memory cells being designated as a defined region having a known defect pattern. A method of validating a memory device includes writing, using a controller in a playback device, a known data pattern to a defined region in the memory device, reading, with the controller, a read data pattern from the defined region, comparing, at the controller, the read data pattern to an expected data pattern, the expected data pattern derived from the known data pattern and a defect map of the defined region, and validating, with the controller, the memory device based upon a correlation result from the comparing.


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