The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Sep. 25, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Srinivas Lingam, Allen, TX (US);

Seok-Jun Lee, Allen, TX (US);

Johann Zipperer, Unterschleissheim, DE;

Manish Goel, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 15/80 (2013.01); G06F 9/30014 (2013.01); G06F 9/30094 (2013.01); G06F 9/30145 (2013.01); G06F 9/325 (2013.01); G06F 9/3822 (2013.01); G06F 9/3853 (2013.01); G06F 9/3877 (2013.01);
Abstract

Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.


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