The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Dec. 20, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Mario Blaum, San Jose, CA (US);

Aayush Gupta, San Jose, CA (US);

James Hafner, Pacific Grove, CA (US);

Steven R. Hetzler, Los Altos, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1076 (2013.01); G06F 3/064 (2013.01); G06F 3/067 (2013.01); G06F 3/0619 (2013.01);
Abstract

A method for memory page erasure-correcting property generation in a storage array includes dividing data into multiple stripes for storage in a storage array including multiple storage devices with a topology of a hypercube of a dimension t≥3. The storage devices in same hypercubes of dimension t−1 including the hypercube of dimension t have even parity. An intersection of two non-parallel planes in the hypercube topology is a line, and each point along a line is a storage device in the storage array. Erasure-correcting properties are generated for the data using three nested codes, wherein a first nested code has even parity over planes of class 0, 1 and 2, a second nested code has a first global parity, and a third nested code has a second global parity and a third global parity.


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