The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Jan. 16, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Saravanan Sethuraman, Bangalore, IN;

Diyanesh B. Chinnakkonda Vidyapoornachary, Bangalore, IN;

Sridhar Rangarajan, Bangalore, IN;

Kirk D. Peterson, Jericho, VT (US);

John B. Deforge, Barre, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 5/06 (2006.01); G11C 29/52 (2006.01); G11C 5/02 (2006.01); G11C 29/42 (2006.01); G11C 29/02 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 3/0604 (2013.01); G06F 3/0625 (2013.01); G06F 3/0631 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01); G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 29/028 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01); G11C 5/025 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.


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