The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Sep. 25, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jie Zheng, Poughkeepsie, NY (US);

Stephen J. Powell, Austin, TX (US);

Steven R. Carlough, Poughkeepsie, NY (US);

Susan M. Eickhoff, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 3/06 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/061 (2013.01); G06F 3/067 (2013.01); G06F 13/161 (2013.01); G06F 13/1689 (2013.01); G06F 13/4022 (2013.01);
Abstract

An Address and Command chip of a distributed memory system includes a memory controller, a first communication link, and one or more interface schedulers, where the one or more interface schedulers include a first interface scheduler residing communicatively between the memory controller and the first communication link. The first interface scheduler is configured to receive a first communication directed from the memory controller to the first communication link; capture the first communication before the first command reaches the first communication link; postpone the first communication for a first set of one or more memory cycles; and reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed.


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