The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2020
Filed:
Nov. 30, 2017
Applicant:
Postech Academy-industry Foundation, Pohang-si, KR;
Inventors:
Jae Yoon Sim, Pohang-si, KR;
Hwa Suk Cho, Daejeon, KR;
Assignee:
POSTECH ACADEMY-INDUSTRY FOUNDATION, Pohang-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/10 (2006.01); G06F 1/03 (2006.01); H03L 7/081 (2006.01); H03L 7/083 (2006.01); H03L 7/197 (2006.01);
U.S. Cl.
CPC ...
G06F 1/0321 (2013.01); H03L 7/083 (2013.01); H03L 7/0818 (2013.01); H03L 7/1976 (2013.01); H03L 2207/50 (2013.01);
Abstract
The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system. The present invention suggests a new structure based on a hardware description language (HDL), and thus reduces a chip area of a frequency synthesizer while obtaining a wide frequency operation range. Furthermore, since only the HDL is used, the entire frequency synthesizer becomes all-synthesizable, and auto layout (auto P&R) can be achieved through a tool, which makes it possible to reduce a design cost of a designer.