The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Nov. 02, 2018
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Rkia Achehboune, Edinburgh, GB;

Dimitris Drogoudis, Edinburgh, GB;

Roberto Brioschi, Austin, TX (US);

Aleksey Sergeyevich Khenkin, Nashua, NH (US);

David Patten, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04R 19/04 (2006.01); B81B 7/02 (2006.01); H04R 1/04 (2006.01); H04R 19/00 (2006.01);
U.S. Cl.
CPC ...
H04R 19/04 (2013.01); B81B 7/02 (2013.01); H04R 1/04 (2013.01); H04R 19/005 (2013.01); B81B 2201/0257 (2013.01); H04R 2201/003 (2013.01);
Abstract

A package for a MEMS device, the package comprising a MEMS transducer within a chamber of the package; and a package substrate, wherein an upper surface of the package substrate defines at least part of a surface of the chamber; wherein the package substrate comprises a plurality of metal layers, the package substrate further comprising at least a part of a filter circuit for filtering RF signals, wherein a first metal layer is provided in a first plane of the substrate and wherein a resistor of the filter circuit is provided in a plane below the first plane.


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