The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Jul. 31, 2019
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Buddhika Abesingha, Escondido, CA (US);

Merlin Green, San Diego, CA (US);

Assignee:

pSemi Corporation, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/14 (2014.01); H03K 5/1534 (2006.01); H03K 17/689 (2006.01); H03K 19/0185 (2006.01); H02M 1/38 (2007.01); H02M 7/538 (2007.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/14 (2013.01); H02M 1/38 (2013.01); H02M 7/538 (2013.01); H03K 5/1534 (2013.01); H03K 17/689 (2013.01); H03K 19/018514 (2013.01); H03K 2005/00019 (2013.01);
Abstract

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.


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