The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Apr. 04, 2018
Applicants:

SK Hynix Inc., Icheon, KR;

Northeastern University, Boston, MA (US);

Inventors:

Hae Kang Jung, Gwangmyeong, KR;

Yong Suk Choi, Seoul, KR;

Yong Bin Kim, Franklin, MA (US);

Gyunam Jeon, Yongin, KR;

Dae-Han Kwon, Icheon, KR;

Joo Hwan Cho, Icheon, KR;

Assignees:

SK hynix Inc., Icheon, KR;

NORTHEASTERN UNIVERSITY, Boston, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/02 (2006.01); H03F 3/19 (2006.01); H03G 3/30 (2006.01); H04B 1/16 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0205 (2013.01); H03F 3/19 (2013.01); H03G 3/3036 (2013.01); H03K 3/356 (2013.01); H04B 1/16 (2013.01); H03F 2200/129 (2013.01); H03F 2200/87 (2013.01);
Abstract

A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.


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