The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Jun. 27, 2018
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Cory B. Arnold, Tempe, AZ (US);

Ilija Jergovic, Palo Alto, CA (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 1/088 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/158 (2013.01); H02M 1/088 (2013.01); H02M 2001/0048 (2013.01);
Abstract

A multi-level switching power converter includes a string of N upper transistors and a string of N lower transistors, where N is an integer greater than one. The N upper transistors are electrically coupled in series between a first power node and a switching node, and the N lower transistors are electrically coupled in series between the switching node and a reference node. The multi-level switching power converter further includes N−1 flying capacitors, an inductor, a bypass transistor, and a controller. The bypass transistor is electrically coupled between the switching node and the reference node. The controller is configured to (a) control switching of the N upper transistors and the N lower transistors and (b) cause the bypass transistor to operate in its on state in response to all of the N lower transistors operating in their respective on states.


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