The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Oct. 30, 2017
Applicant:

Commscope Technologies Llc, Hickory, NC (US);

Inventor:

Bernard Harold Hammond, Jr., Cheltenham, GB;

Assignee:

CommScope Technologies LLC, Hickory, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 24/00 (2011.01); H01R 13/6466 (2011.01); H01R 13/6474 (2011.01); H01R 24/64 (2011.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H01R 13/6466 (2013.01); H01R 13/6474 (2013.01); H01R 24/64 (2013.01); H05K 1/0213 (2013.01); H05K 2201/10189 (2013.01);
Abstract

A telecommunications connector includes a housing defining a port for receiving a plug. A circuit board has a first conductive layer and a second conductive layer, with a dielectric layer situated between the first and second conductive layers. A plurality of conductive vias extend through the circuit board, and receive a plurality of electrical connection members and a plurality of wire termination contacts. A plurality of conductive tracks electrically interconnect selected ones of the plurality of conductive vias so as to electrically connect the plurality of electrical connection members and the plurality of wire termination contacts. A crosstalk compensation arrangement provides crosstalk compensation between selected conductive tracks of the circuit board. The crosstalk compensation arrangement includes a first capacitive coupling having a first conductive plate on the first conductive layer and a second conductive plate on the second conductive layer, and a first one of the conductive vias is at least partially surrounded by the first conductive plate. The first conductive plate on the first conductive layer may further form a second capacitive coupling with third conductive plate on the second conductive layer.


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