The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10734475 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 04, 2020

Filed:

Apr. 03, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takashi Ando, Tuckahoe, NY (US);

Robert Allen Groves, Highland, NY (US);

Hemanth Jagannathan, Niskayuna, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Griselda Bonilla, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 28/75 (2013.01); H01L 21/76804 (2013.01); H01L 21/76831 (2013.01); H01L 21/76879 (2013.01); H01L 23/5223 (2013.01); H01L 27/0805 (2013.01);
Abstract

A method is presented for forming a stacked metal-insular-metal (MIM) capacitor with self-aligned contact. The method includes forming a first electrode plate over a first interlayer dielectric (ILD), forming a first spacer adjacent the first electrode plate, forming a first insulating layer over the first electrode plate, forming a second electrode plate over the first insulating layer, and forming a second spacer adjacent the second electrode plate and the first insulating layer. The method further includes forming a second insulating layer over the second electrode plate, forming a third electrode plate over the second insulating layer, forming a third spacer adjacent the third electrode plate and the second insulating layer, and forming a second ILD over the third electrode plate. The method also includes forming a first via through the second ILD and directly contacting the second spacer such to prevent the first via from contacting the second electrode plate.


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