The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Feb. 28, 2019
Applicant:

Samsung Display Co., Ltd., Yongin-Si, Gyeonggi-Do, KR;

Inventors:

Il Joo Kim, Yongin-si, KR;

Cheol Gon Lee, Yongin-si, KR;

Mee Hye Jung, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 27/32 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); G09G 3/32 (2016.01); G09G 3/3225 (2016.01); G09G 3/3233 (2016.01);
U.S. Cl.
CPC ...
H01L 27/3272 (2013.01); G09G 3/32 (2013.01); G09G 3/3225 (2013.01); G09G 3/3233 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/3262 (2013.01); H01L 27/3265 (2013.01); H01L 27/3276 (2013.01); H01L 29/78633 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01);
Abstract

A display device includes: a substrate; a plurality of pixels provided in a pixel region of the substrate; a scan line and a data line, connected to each of the plurality of pixels; a first transistor connected to the scan line and the data line and a second transistor connected to the first transistor; a light emitting element connected to the transistor; a first blocking layer disposed between the substrate and the first transistor, the first blocking layer being electrically connected to the first transistor; and a second blocking layer disposed between the substrate and the second transistor, the second blocking layer being electrically connected to the second transistor, wherein the first blocking layer is connected to a gate electrode of the first transistor, and the second blocking layer is connected to any one of source and drain electrodes of the second transistor.


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