The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Aug. 31, 2016
Applicant:

Aisin Aw Co., Ltd., Anjo-shi, Aichi-ken, JP;

Inventor:

Takanobu Naruse, Nishio, JP;

Assignee:

AISIN AW CO., LTD., Anjo-shi, Aichi-Ken, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); G11C 5/04 (2006.01); G01C 21/36 (2006.01); H01L 25/18 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 25/04 (2014.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); G01C 21/3688 (2013.01); G11C 5/04 (2013.01); H01L 23/498 (2013.01); H01L 24/49 (2013.01); H01L 25/04 (2013.01); H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

Input and output terminals are arranged so as to be adapted for an environment in which they are to be used. A semiconductor module () is surface-mounted on a surface wiring layer () of a main substrate (). A first module terminal group () located on a module first side () of the semiconductor module () and a first substrate terminal group () located on a substrate first side () of the main substrate () are connected by a first surface wiring pattern () formed in a surface wiring layer (). A second module terminal group () located on a module second side () and a second substrate terminal group () located on a substrate second side () are connected by a second surface wiring pattern () formed in the surface wiring layer ().


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