The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2020
Filed:
May. 31, 2019
Applicant:
Western Digital Technologies, Inc., San Jose, CA (US);
Inventors:
Narayan Kuddannavar, Bangalore, IN;
Swaroop Kaza, Milpitas, CA (US);
Sainath Viswasarai, Bangalore, IN;
Assignee:
Western Digital Technologies, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract
A non-volatile storage system comprises non-volatile memory cells arranged in physical blocks, and one or more control circuits in communication with the non-volatile memory cells. The one or more control circuits are configured to write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold.