The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Dec. 13, 2018
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Mostafa El Gamal, Worcester, MA (US);

Niranjay Ravindran, Rochester, MN (US);

James Fitzpatrick, Laguna Niguel, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); H03K 23/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); H03K 23/005 (2013.01); G11C 2211/562 (2013.01); G11C 2211/5641 (2013.01); G11C 2211/5644 (2013.01);
Abstract

Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.


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