The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Sep. 26, 2019
Applicant:

Uniquify Ip Company, Llc, San Francisco, CA (US);

Inventors:

Mahesh Gopalan, Milpitas, CA (US);

David Wu, Saratoga, CA (US);

Venkat Iyer, Sunnyvale, CA (US);

Assignee:

UNIQUIFY IP COMPANY, LLC, San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01); G06F 12/06 (2006.01); G06F 1/04 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); G06F 1/14 (2006.01); G11C 11/4093 (2006.01); G11C 7/04 (2006.01); G11C 11/40 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/04 (2013.01); G06F 1/08 (2013.01); G06F 1/12 (2013.01); G06F 1/14 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 3/0619 (2013.01); G06F 12/0646 (2013.01); G06F 13/1689 (2013.01); G06F 13/4243 (2013.01); G11C 7/1072 (2013.01); G11C 7/222 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 7/04 (2013.01); G11C 11/40 (2013.01);
Abstract

In accordance with one embodiment, a computer-implemented method is provided, comprising: configuring code to cause at least part of hardware to operate as a double data rate (DDR) memory controller and to produce one or more capture clocks, where: a timing of at least one of the one or more capture clocks is based on a first clock signal of a first clock, the first clock signal is a core clock signal or a signal derived from at least the core clock signal, the at least one of the one or more capture clocks is used to time a read data path, the at least one of the one or more capture clocks is used to capture read data into a clock domain related to a second clock, the first clock and the second clock being related in timing such that at least one of: the second clock is derived from the first clock, or the first clock is derived from the second clock; and providing access to the code.


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