The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Sep. 27, 2018
Applicant:

National Tsing Hua University, Hsinchu, TW;

Inventors:

Meng-Fan Chang, Taichung, TW;

Huan-Ting Lin, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 7/08 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 7/12 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 7/08 (2013.01); G11C 7/065 (2013.01); G11C 7/12 (2013.01); G11C 11/1655 (2013.01); G11C 11/1673 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 2013/005 (2013.01);
Abstract

A voltage-enhanced-feedback sense amplifier of a resistive memory is configured to sense a first bit line and a second bit line. The voltage-enhanced-feedback sense amplifier includes a voltage sense amplifier and a voltage-enhanced-feedback pre-amplifier. The voltage-enhanced-feedback pre-amplifier is electrically connected to the voltage sense amplifier. A first bit-line amplifying module receives a voltage level of the second input node to suppress a voltage drop of the first bit line and amplifies a voltage level of the first input node according to a voltage level of the first bit line. A second bit-line amplifying module receives the voltage level of the first input node to suppress a voltage drop of the second bit line and amplifies the voltage level of the second input node according to a voltage level of the second bit line. A margin enhanced voltage difference is greater than a read voltage difference.


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