The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Oct. 22, 2018
Applicants:

Samsung Display Co., Ltd., Yongin-Si, Gyeonggi-Do, KR;

Industry-university Cooperation Foundation Hanyang University, Seoul, KR;

Inventors:

Chongchul Chai, Seoul, KR;

Ansu Lee, Seoul, KR;

Boyong Chung, Suwon-si, KR;

Oh-Kyong Kwon, Seoul, KR;

Nack-Hyeon Keum, Daegu, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3291 (2016.01); G09G 3/3233 (2016.01); H01L 27/32 (2006.01); G09G 3/3258 (2016.01); G09G 3/3266 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3291 (2013.01); G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); H01L 27/3276 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0439 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0238 (2013.01); G09G 2320/043 (2013.01);
Abstract

A pixel includes a first transistor connected between a line supplying a power supply voltage and a second node, and providing a driving current corresponding to a data voltage to a light emitting element based on a voltage of a first node, a third transistor connected between the first node and a line supplying a reference voltage, and generating a sampling current based on a difference between a voltage of the second node and the reference voltage, a second transistor connected between the line supplying the power supply voltage and the first node, adjusting the voltage of the first node to generate the sampling current based on a voltage of a third node, a fourth transistor transferring the power supply voltage to the third node, a fifth transistor transferring the data voltage to the second node, and a capacitor connected between the first node and the third node.


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