The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Jul. 27, 2018
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Hao Xiao, Nanjing, CN;

Yuangang Wang, Shenzhen, CN;

Jun Xu, Nanjing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0815 (2016.01); G06F 9/46 (2006.01); G06F 9/52 (2006.01); G06F 12/0806 (2016.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 9/46 (2013.01); G06F 9/467 (2013.01); G06F 9/52 (2013.01); G06F 12/0806 (2013.01); G06F 12/0833 (2013.01); G06F 2212/27 (2013.01); G06F 2212/283 (2013.01); G06F 2212/50 (2013.01); G06F 2212/62 (2013.01);
Abstract

A processing node, a computer system, and a transaction conflict detection method, where the processing node includes a processor and a transactional cache. When obtaining a first operation instruction in a transaction for accessing shared data, the processor accesses the transactional cache for caching shared data of a transaction processed by the processing node. If the transactional cache determines that the first operation instruction fails to hit a cache line in the transactional cache, the transactional cache sends a first destination address in the operation instruction to a transactional cache in another processing node. After receiving status information of a cache line hit by the first destination address from the other processing node, the transactional cache determines, based on the received status information, whether the first operation instruction conflicts with a second operation instruction executed by the other processing node.


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